1. Field of the Invention
The present invention generally relates to a memory system, and in particular, to a system and method for controlling the direction of data flow in a memory system having a buffering structure interconnecting a memory controller and memory devices. The memory devices may, for example, be dynamic random access memory (DRAM) devices.
2. Related Art
A typical memory system includes a memory controller and memory devices, such as DRAMs, coupled thereto. In some systems, a processor performs memory controller functions. As used herein, the term memory controller includes such a processor. FIG. 1 illustrates a prior art memory system having memory devices 80-95 residing on memory modules. The memory modules are connected to a memory controller 50 via connectors 60, 70. In such a system, it is required that each component operates with the same interface voltage and frequency. Therefore, the memory controller 50 is manufactured to operate with specific memory devices 80-95 meeting these parameters. Conversely, the memory devices 80-95 are also utilized only with a memory controller 50 having the same interface voltage and operating frequency. Therefore, the memory devices 80-95 utilized with memory controllers are limited to only those having the same interface voltage and operating frequency as that of the memory controller 50.
FIG. 2 shows the bi-directional nature of communication exchanges in a memory interface. The memory interface may be a data bus 52, which may represent, address bus lines, command signal lines, and/or data bus lines. The data bus 52 of the memory interface is bi-directional since a memory system has to be able to write data and read data on the same pins connecting the memory controller 50 and the memory devices 80-95. The memory controller 50 includes a bi-directional internal input/output buffer. The memory devices 80-95 also have bi-directional internal input/output buffers. When the memory controller 50 is doing a read or a write, it has complete knowledge of the read and write. That is, the memory controller 50 knows when to turn off its driver and listen to its input internal buffer. Similarly, the memory devices 80-95 also have complete knowledge of when to turn off their drivers and listen to their internal buffers based on the commands that they receive and the function(s) to be performed. Because both the memory controller 50 and the memory devices 80-95 are able to control the direction of their own internal buffers automatically, the direction of data flow between the memory controller 50 and the memory devices 80-95 can be readily controlled. However, the memory devices 80-95 are limited to only those having the same interface voltage and operating frequency as that of the memory controller 50. The cost requiring specifically designed memory devices 80-95 to match the memory controller 50, and vice versa, creates enormous development expenses, as well as limiting the interchangeability of various existing memory components.
In other memory systems, solutions have evolved to provide connection to memory devices on selective bases. For example, in a Double Data Rate-Synchronous DRAM (DDR), located on the module are field effect transistor (FET) switches which isolate the DRAM from the main memory bus. This isolates the capacitive load. The FET switches are turned on t o connect the DRAM to the memory bus only when the DRAM is being read or written. When the FET switches are to be turned on, the DRAM sends out a control signal. This method focuses on using a special kind of DRAM and does not deal with the flow direction of the data. The FETs as a whole are merely acting as a switch that connects the DRAM to the memory bus. Therefore, there is a need for a system and method to control the direction of data flow in a memory system that would not require each component to operate with the same interface voltage and frequency.